The invention relates to computer systems and in particular to processors that detect overlapping instruction groups and adjust processing in response.
The present application is related to the following U.S. Pat. No. 7,010,676.
U.S. Pat. No. 7,010,676 entitled METHOD AND SYSTEM FOR PROCESSING LOOP BRANCH INSTRUCTIONS, which issued on Mar. 7, 2006.
This patent and the present application are owned by one and the same assignee, International Business Machines Corporation of Armonk, N.Y. The descriptions set forth in this patent are hereby incorporated into the present application by reference.
Trademarks: IBM® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. S/390, Z900 and z990 and other product names may be registered trademarks or product names of International Business Machines Corporation or other companies.
Existing computer systems detect a match between an opcode about to be executed and opcodes programmed into it by the computer manufacturer to alleviate design deficiencies in the processor. One such system is disclosed in U.S. Pat. No. 6,092,185, the entire contents of which are incorporated herein by reference. The system has a mechanism to send action(s) to be taken to the I-unit (Instruction fetch and decode unit) upon detection of a predefined opcode.
While well suited for its intended purpose, the prior system is only applicable to single scalar processors when only one instruction is issued. Upon detecting a predefined opcode, the actions taken are severe (serialization, force instruction to be executed in millicode) that result in significant performance degradation if the hardware is allowed to run with these actions.